The present invention generally relates to multiplexer circuits and in particular to a multiplexer circuit for producing a plurality of output voltages selectively in response to control data.
In the semiconductor integrated circuits, efforts are made to reduce the number of devices in the circuit and hence the cost of the integrated circuit while maintaining the full function of the circuit. The multiplexer circuit for use in the mobile telephones such as portable telephones or automobile telephones is no exception.
FIG. 1 is a circuit diagram showing a conventional multiplexer circuit that is used in the portable telephones.
Referring to FIG. 1, an input radio frequency signal RF.sub.in is supplied to an input terminal 11a of a power amplifier 11 for amplification, and the power amplifier 11 produces an output signal RF.sub.out at an output terminal 11b. Further, the power amplifier 11 has a control terminal 11c for receiving a gain control signal VAPc, and the gain of the power amplifier 11 is controlled in response to the gain control signal VAPc at the control terminal 11c.
In order to control the gain of the power amplifier 11, there is provided a differential amplifier 12 having a non-inverting input terminal to which the output signal RF.sub.out is supplied from the power amplifier 11 after rectification and smoothing in a diode 12a and an RC filter circuit 12b. The differential amplifier 12 is further supplied with a reference signal MPOUT at an inverting input terminal thereof, and produces the gain control signal VAPc in response to the difference between the signal at the non-inverting input terminal and the signal at the inverting input terminal.
The reference signal MPOUT is produced by a multiplexer circuit 13 that is supplied with external control data CONTROL at input terminals c.sub.1, c.sub.2 and c.sub.3 in response to the combination of the logic states of the control data. Thus, the level of the reference signal MPOUT is changed and the level of the control signal VAPc is changed in response thereto. In other words, the power amplifier 11 of FIG. 1 produces the output signal RFOUT with a variable gain that is specified by the control data at the input terminals c.sub.1 -c.sub.3 of the multiplexer circuit 13.
In the illustrated example, the control data supplied to the multiplexer 13 is the three-bit data in correspondence to the three input terminals c.sub.1 -c.sub.3. In response to the eight possible combinations specified by the three-bit data, there are eight reference voltages v.sub.1 -v.sub.8 that are produced by the voltage-dividing function of a reference voltage V.sub.REF by resistors X.sub.1 -X.sub.8 and supplied to the multiplexer 13. Thus, the output level of the signal RFout can be changed by eight possible levels. Of course, the number of bits of the control data CONTROL is not limited to three.
FIG. 2 shows the circuit construction employed conventionally for the multiplexer 13. In this example, it should be noted that there are only two input terminals, c1 and c2, for the control data CONTROL. Thus, the circuit of FIG. 1 that uses the multiplexer of FIG. 2 is capable of changing the gain of the power amplifier 11 by only four levels. In correspondence to the four levels for the gain adjustment, there are four reference voltages v.sub.1 -v.sub.4 instead of eight reference voltages v.sub.1 -v.sub.8 of FIG. 1.
Referring to FIG. 2, there are four input terminals Ti.sub.1 -Ti.sub.4 in correspondence to four circuits 1a-1d for receiving the four reference voltages v.sub.1 -v.sub.4. In correspondence to each input terminal there is an NPN transistor for receiving the reference voltage at a base thereof. For example, the input terminal Ti.sub.4 of the circuit 1d is connected to a base of an NPN transistor Tr.sub.1. The NPN transistor Tr.sub.1 has an emitter connected to an emitter of a PNP transistor Tr.sub.2 that forms a current mirror circuit together with another PNP transistor Tr.sub.3.
The PNP transistors Tr.sub.2 and Tr.sub.3 have respective bases connected commonly with each other to an emitter of an NPN transistor Tr.sub.5 that in turn forms another current mirror circuit with an NPN transistor Tr.sub.4. There, the transistor Tr.sub.4 and the transistor Tr.sub.5 have respective bases connected commonly to a constant current source 2a and respective emitters connected commonly to the ground. Thereby, the transistors Tr.sub.4 and Tr.sub.5 are normally turned on by the base current supplied from the constant current source 2a, unless the base of the transistors Tr.sub.4 and Tr.sub.5 is connected to the ground. When the transistor Tr.sub.5 is turned on, the transistors Tr.sub.2 and Tr.sub.3 are turned on because of the increased base-emitter voltage.
Further, the transistor Tr.sub.1 has a collector connected to a collector of a PNP transistor Tr.sub.6 that in turn has a base connected to its collector and an emitter connected to a voltage source Vcc. The transistor Tr.sub.3 has an emitter connected to the emitter of an NPN transistor Tr.sub.9 that in turn has a base connected to an output terminal to for outputting the signal MPOUT and further to the ground via another current source 2b. The transistor Tr.sub.9 has a collector that is connected to a collector of a PNP transistor 7 that forms a current mirror together with the PNP transistor Tr.sub.6. Thus, the transistor Tr.sub.7 has a base connected commonly to the base and hence the collector of the transistor Tr.sub.6, and an emitter connected to the voltage source Vcc. Further, there is another transistor Tr.sub.8 that has a collector connected to the voltage source Vcc, a base connected on the one hand to the collector of the transistor Tr.sub.7 and on the other hand to the collector of the transistor Tr.sub.9, and an emitter connected on the one hand to the base of the transistor Tr.sub.9 and on the other hand to the ground via the constant current source 2b.
In operation, the transistor Tr.sub.1 is turned on in response to the input voltage v.sub.4 and in turn induces the turning-on of the transistors Tr.sub.6 and Tr.sub.7. Here, it is assumed that the transistors Tr.sub.2 -Tr.sub.5 are in the turned-on state. In response to the turning-on of the transistor Tr.sub.1, the transistors Tr.sub.6 and Tr.sub.7 are turned on, and in response to the turning-on of the transistor Tr.sub.7, the transistors Tr.sub.8 and Tr.sub.9 are turned on. In this state, the sum of the voltage drops caused across the base and emitter of the transistors Tr.sub.1 and Tr.sub.2 becomes equal to the sum of the voltage drops across the base and emitter of the transistors Tr.sub.3 and Tr.sub.9. In other words, a voltage equal to the voltage v.sub.4 is obtained at the output terminal To as the voltage MPOUT. As the construction and operation for other circuits 1a-1c are identical with those described above, the description thereof will be omitted.
In order to obtain one of the voltages v.sub.1 -v.sub.4 selectively at the output terminal To as the output voltage MPOUT, a decoder circuit 3 is connected for selectively enabling one of the circuits 1a-1d. The decoder circuit includes transistors Tr.sub.11 and Tr.sub.12 having respective bases connected to the input terminals c.sub.1 and c.sub.2. The transistor Tr.sub.11 has a collector connected to the voltage source Vcc via a constant current source 2c and an emitter connected to the ground, while the transistor Tr.sub.12 has a collector connected to the voltage source Vcc via a constant current source 2d and an emitter connected to the ground. Further, in order to enable the circuits 1a-1d, transistors Tr.sub.13 -Tr.sub.20 are provided, wherein the transistors Tr.sub.13 and Tr.sub.14 selectively enable the circuit 1a, the transistors Tr.sub.15 and Tr.sub.16 selectively enable the circuit 1b. the transistors Tr.sub.17 and Tr.sub.18 selectively enable the circuit 1c, and the transistors Tr.sub.19 and Tr.sub.20 selectively enable the circuit 1d.
It should be noted that the transistors Tr.sub.19 and Tr.sub.20 have bases respectively connected to the collector of the transistor Tr.sub.11 and the collector of the transistor Tr.sub.12. Further, collectors of the transistors Tr.sub.19 and Tr.sub.20 are connected commonly to the bases of the transistors Tr.sub.4 and Tr.sub.5. Emitters of the transistors Tr.sub.19 and Tr.sub.20 in turn are connected commonly to the ground. Thereby, at least one of the transistors Tr.sub.19 and Tr.sub.20 is turned on when the logic level of the control data CONTROL at the input terminals c.sub.1 and c.sub.2 is any of (L, L), (H, L), and (L, H), where the first letter in the parentheses represents the logic level of the input terminal c.sub.1, the second letter in the parentheses represents the logic level of the input terminal c.sub.2, L represents the low level state, and H represents the high level state. Only when the control data has the state (H, H) are the transistors Tr.sub.19 and Tr.sub.20 both turned off. This means that the respective bases of the transistors Tr.sub.4 and Tr.sub.5 are both grounded unless there is the control data (L, L) at the input terminals c.sub.1 and c.sub.2. In other words, the foregoing operation of the circuit 1d to produce the voltage v.sub.4 at the output terminal To is obtained only when the input control data CONTROL has the high level state H at both input terminals c.sub.1 and c.sub.2. Otherwise, the base of the transistors Tr.sub.4 and Tr.sub.5 is held at the ground level. Similarly, the circuits 1a-1c are selectively enabled in response to the combination of the logic levels of the bits of control data CONTROL at the input terminals c.sub.1 and c.sub.2.
This circuit of FIG. 2 has an obvious problem of a complex circuit construction and a large number of parts. It will be easily understood that the number of transistors in the decoder circuit 3 increases steeply with an increasing number of different voltage levels in the output voltage MPOUT. For example, when there are three input terminals c.sub.1 -c.sub.3 in correspondence to the three-bit control data as illustrated in FIG. 1, one needs twenty-seven transistors in the decoder 3 as compared to the ten transistors Tr.sub.11 -Tr.sub.20 in the example of FIG. 2. It should be noted that the increase in the number of transistors occurs also in the circuits 1a, 1b, . . . . Thus, the conventional multiplexer circuit has suffered from the problem that the number of voltage levels that are selectively produced is limited.